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| CDB43L43 Evaluation Board for CS43L43 Rev D Features l Demonstrates Description The CDB43L43 evaluation board is an excellent means for quickly evaluating the CS43L43 24-bit, stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the CS43L43 (for control port mode only) and a power supply. Analog headphone outputs are provided via a 1/8" headphone jack and RCA phono jacks. The CS8415A digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog converter and will accept AES/EBU, S/PDIF, and EIAJ340 compatible audio data. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development. ORDERING INFORMATION CDB43L43 Evaluation Board recommended layout and grounding arrangements l CS8415A receives AES/EBU, S/PDIF, and EIAJ-340 Compatible Digital Audio l Patch Area l Requires only a digital signal source and power supplies for a complete Digital-toAnalog-Converter system I/O for Clocks and Data Control Port Microcontroller Control Port Interface CS8415A Digital Audio Interface CS43L43 Headphone Outputs Preliminary Product Information P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright (c) Cirrus Logic, Inc. 2000 (All Rights Reserved) JUN `00 DS479DB1 1 CDB43L43 TABLE OF CONTENTS 1. CDB43L43 SYSTEM OVERVIEW .................................................................. 3 2. CS43L43 DIGITAL TO ANALOG CONVERTER ............................................ 3 3. CS8415A DIGITAL AUDIO RECEIVER ......................................................... 3 4. CS8415A DATA FORMAT ............................................................................. 3 5. HEADPHONE OUTPUT .................................................................................. 3 6. INPUT/OUTPUT FOR CLOCKS AND DATA ................................................. 3 7. POWER SUPPLY CIRCUITRY ....................................................................... 3 8. GROUNDING AND POWER SUPPLY DECOUPLING .................................. 4 9. CONTROL PORT SOFTWARE ...................................................................... 4 10. POPGUARD(R) WORKAROUND .................................................................. 4 11. CDB43L43 PERFORMANCE PLOTS ......................................................... 4 12. CDB43L43 REV A ERRATA ....................................................................... 4 LIST OF FIGURES Figure 1. System Block Diagram and Signal Flow .............................................. 6 Figure 2. CS43L43 .............................................................................................. 7 Figure 3. Headphone Outputs ............................................................................. 8 Figure 4. CS8415A Digital Audio Receiver ......................................................... 9 Figure 5. Digital Audio Inputs ............................................................................ 10 Figure 6. MCLK Divider and Level Shifter ......................................................... 11 Figure 7. Control Port Interface ......................................................................... 12 Figure 8. Control Port Microcontroller ............................................................... 13 Figure 9. Control Port Level Shifter ................................................................... 14 Figure 10.I/O for Clocks and Data ...................................................................... 15 Figure 11.Reset Circuit ....................................................................................... 16 Figure 12.Power Supply ..................................................................................... 17 Figure 13.Frequency Response at 1.8 V ............................................................ 18 Figure 14.Frequency Response at 3.0 V ............................................................ 18 Figure 15.THD+N versus Amplitude at 1.8 V ..................................................... 18 Figure 16.THD+N versus Amplitude at 3.0 V ..................................................... 18 Figure 17.FFT of 1 kHz Sine Wave at 1.8 V ....................................................... 18 Figure 18.FFT of 1 kHz Sine Wave at 3.0 V ....................................................... 18 Figure 19.Silkscreen Top ................................................................................... 19 Figure 20.Bottom Side ........................................................................................ 20 Figure 21.Top Side ............................................................................................. 21 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com. 2 DS479DB1 CDB43L43 1. CDB43L43 SYSTEM OVERVIEW The CDB43L43 evaluation board is an excellent means of quickly evaluating the CS43L43. The CS8415A digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system development. The CDB43L43 schematic has been partitioned into 10 schematics shown in Figures 2 through 11. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the the system diagram also includes the interconnections between the partitioned schematics. 5. HEADPHONE OUTPUT A 1/8 inch, stereo headphone jack is included on the evaluation board for connecting 16 ohm or greater headphones to the CS43L43. If no headphones are connected to the 1/8 inch jack, then a 16 ohm resistor is connected to each of the CS43L43 headphone outputs, HP_A and HP_B. This is useful when evaluating the CS43L43 headphone amplifier with test equipment that has high-impedance inputs. RCA jacks are also provided on the headphone outputs for easy connection to test equipment. 6. INPUT/OUTPUT FOR CLOCKS AND DATA The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, HDR1. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure 10. 2. CS43L43 DIGITAL TO ANALOG CONVERTER A description of the CS43L43 is included in the CS43L43 datasheet. 3. CS8415A DIGITAL AUDIO RECEIVER The system receives and decodes the standard S/PDIF data format using a CS8415A Digital Audio Receiver, Figure 4. The outputs of the CS8415A include a serial bit clock, serial data, leftright clock (FSYNC), de-emphasis control and a 256 Fs master clock. The operation of the CS8415A and a discussion of the digital audio interface are included in the CS8415A datasheet. The evaluation board has been designed such that the input can be either optical or coax, see Figure 5. However, both inputs cannot be driven simultaneously. 7. POWER SUPPLY CIRCUITRY Power is supplied to the evaluation board by five binding posts (GND, +5 V, VL, VA, VA_HP), see Figure 12. The +5 V input supplies power to the +5 Volt digital circuitry (VA_+5, VD_+5), while the VL input supplies power to the Voltage Level Converters and the CS43L43 VL pin. VA and VA_HP supply power to the CS43L43. For ease of use, it is possible to connect VA, VA_HP and VL to the same supply. WARNING: VA and VL must be between +1.7 V and +3.6 V. VA_HP must be between +0.9 V and +3.6 V. Operation outside of this range can cause permanent damage to the device. See the CS43L43 datasheet for more details. 4. CS8415A DATA FORMAT The CS8415A data format is selected through the DIP switch. See Table 2 for details. DS479DB1 3 CDB43L43 8. GROUNDING AND POWER SUPPLY DECOUPLING The CS43L43 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 9 details the power distribution used on this board. The decoupling capacitors are located as close to the CS43L43 as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yields large reductions in radiated noise. to Figure 3. To bypass this hardware fix, stuff R18 and R19 with 0 ohm resistors and change R25 and R26 to 1 kohm resistors. The next silicon revision will address this issue. 11. CDB43L43 PERFORMANCE PLOTS The CDB43L43 Rev A performance plots shown in Figures 13 through 18 were generated using an Audio Precision System Two Cascade with the S2AES17LP 20 kHz brickwall filter applied. All tests were performed at a sampling rate of 48 kHz and with VL, VA, and VA_HP set to the indicated voltage supply. 9. CONTROL PORT SOFTWARE The CDB43L43 is shipped with Windows based software for interfacing with the CS43L43 control port via the serial connector, J1. The software can be used to communicate with the CS43L43 in Two Wire mode. Note: DIP 2-4 must be set appropriately for control port mode operation. 12. CDB43L43 REV A ERRATA 1) R20 and R30 have been stuffed with 0 ohm resistors and 47 kohm pull-downs have been added to pins 3 and 28 of U4. 2) The DIP switch has been turned such that the "open" position is denoted by the "1" on the board. 3) R31 has been changed from a pull-up to a pulldown. 4) A 1 Mohm pull-down has been added to U10 pin 8, located near R24. 10. POPGUARD(R) WORKAROUND The CDB43L43 Rev A includes a hardware fix for the PopGuard(R) Transient Control feature of the CS43L43 Rev D. Please see the CS43L43 errata for further details. This additional hardware includes the transistors Q1, Q2, Q4, and Q5 as well as R13, R14, R24, R33, R34, and C7. Please refer 4 DS479DB1 CDB43L43 CONNECTOR +5 V VA, VL VA_HP GND Coax Input Optical Input HDR1 Serial Port HDR2 HP_A (J3) HP_B (J2) HP_A&B (J10) INPUT/OUTPUT Input Input Input Input Input Input Input/Output Input/Output Input/Output Output Output Output + 5 Volt power SIGNAL PRESENT + 1.8 Volt to + 3.3 Volt power for the CS43L43 and the Voltage Level Converters +0.9 Volt to +3.3 Volt power for the CS43L43 headphone amp Ground connection from power supply Digital audio interface input via coax Digital audio interface input via optical I/O for master, serial, left/right clocks and serial data Serial connection to PC for Two Wire mode control port signals I/O for Two Wire mode control port signals Channel A headphone output Channel B headphone output Channel A and B headphone output Table 1. System Connections JUMPER Program/Run HRM/BRM EXT/INT SCLK Reset (S1) DIP 1 PURPOSE POSITION FUNCTION SELECTED Programming switch for the con- Program*Run Configures CDB43L43 to program the C trol port microcontroller Configures CDB43L43 for normal operation Seclects High Rate or Base Rate HRM (/2) Mode *BRM (x1) Selects SCLK Mode Resets the CDB43L43 Enable/Disable the CS8415A *0 1 CS8415A is enabled Disabled (External Clocks and Data via HDR1) Control Port mode Stand Alone mode, I2S Stand Alone mode, LJ24 Stand Alone mode, RJ16 (8415A not avail.) Stand Alone mode, RJ24 INT*EXT Selects High Rate Mode Selects Base Rate Mode Internal SCLK Mode External SCLK Mode DIP 2-4 Configures the interface format *000 and CS43L43 operational mode 001 010 011 100 *Default factory settings Note: Table 2. CDB43L43 Jumper and Switch settings DS479DB1 5 6 Control Port Interface Fig 7 Reset DIF0 DIF1 Control Port Microcontroller Fig 8 I/O for Clocks and Data Fig 10 Digital Audio Inputs Fig 5 RXN RXP CS8415A Digital Audio Receiver Connections Fig 4 MCLK LRCK SCLK SDATA Reset Circuit Fig 11 Control Port Level Shifter Fig 9 MCLK Divider and Level Shifter Fig 6 MCLK LRCK SCLK SDATA CS43L43 Fig 2 Headphone Outputs Fig 3 CDB43L43 Figure 1. System Block Diagram and Signal Flow DS479DB1 DS479DB1 CDB43L43 Figure 2. CS43L43 7 8 CDB43L43 Figure 3. Headphone Outputs DS479DB1 DS479DB1 CDB43L43 Figure 4. CS8415A Digital Audio Receiver 9 CDB43L43 Figure 5. Digital Audio Inputs 10 DS479DB1 CDB43L43 Figure 6. MCLK Divider and Level Shifter DS479DB1 11 12 CDB43L43 DS479DB1 Figure 7. Control Port Interface CDB43L43 Figure 8. Control Port Microcontroller DS479DB1 13 14 CDB43L43 Figure 9. Control Port Level Shifter DS479DB1 DS479DB1 CDB43L43 Figure 10. I/O for Clocks and Data 15 16 CDB43L43 Figure 11. Reset Circuit DS479DB1 CDB43L43 Figure 12. Power Supply DS479DB1 17 CDB43L43 +1 +0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 +1 +0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 d B -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 -8.5 -9 20 d B -4 -4.5 -5 -5.5 -6 -6.5 -7 -7.5 -8 -8.5 50 100 200 500 1k 2k 5k 10k 20k -9 20 50 100 200 500 1k 2k 5k 10k 20k Hz Hz Figure 13. Frequency Response at 1.8 V Figure 14. Frequency Response at 3.0 V -81 -81.5 -82 -82.5 -83 -83.5 -84 -84.5 -74 -75 -76 -77 -78 -79 -80 -81 THD+N (dB) -85 -85.5 -86 -86.5 -87 -87.5 -88 -88.5 -89 -89.5 -90 -90.5 -91 -60 THD+N (dB) -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 +0 -82 -83 -84 -85 -86 -87 -88 -89 -90 -91 -92 -93 -94 -60 Amplitude (dB) -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 +0 Amplitude (dB) Figure 15. THD+N versus Amplitude at 1.8 V Figure 16. THD+N versus Amplitude at 3.0 V +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 +0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 d B -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 d B -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -115 -120 -120 -125 -125 -130 20 50 100 200 500 1k 2k 5k 10k 20k Hz -130 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 17. FFT of 1 kHz Sine Wave at 1.8 V Figure 18. FFT of 1 kHz Sine Wave at 3.0 V 18 DS479DB1 DS479DB1 CDB43L43 Figure 19. Silkscreen Top 19 20 CDB43L43 DS479DB1 Figure 21. Bottom Side DS479DB1 CDB43L43 Figure 20. Top Side 21 |
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